Over the last few years, bandwidth requirement of data centers optical interconnection has grown tremendously. Accelerated global internet usage, as well as newly emerging cloud computing, big data and social media applications results in massive capacity requirement of both intra-connections between switches (e.g., top of the rack switches) inside the data-centers element, as well as external inter-connections between different data-centers locations. These optical connections are expected to scale up in speed, and support ultra-high data rates (i.e., 100 Gbit/sec and beyond) under severe constrains of power consumption and cost. In particular, the proposed solutions should be based on existing infrastructure, which includes low-costs and severely bandlimited opto-electronic components such as Digital-to-Analog-Converters (DACs), electrical drivers, modulators, optical receivers and Analog-to-Digital. Converters (ADCs).
One of the existing solutions is a system which incorporates DSP dedicated Integrated Circuits (ICs), which can effectively compensate for the optical fiber and opto-electronic devices impairments. Such system architecture provides a cost effective solution, as it leverages on Moore's ‘law’ for low-cost, low-power consumption and high speed implementation, instead of introducing costly wide-bandwidth opto-electronic components. It was demonstrated that Maximum-Likelihood Sequence Estimation (MLSE) can effectively mitigate the Inter-Symbol-Interference (ISI) resulting from system bandwidth limitation, as well as for different impairments of the optical fiber.
However, a major bottleneck in such a system design is the high-speed and high-resolution ADC device that should meet the system demands. As the analog bandwidth increases, the complexity of high-resolution ADCs circuitry is scaling drastically, resulting in excessive power consumption and extremely high costs. In addition, high-resolution ADCs require corresponding high resolution DSP units, which also increase the system complexity.
One way to overcome this technological challenge is to reduce the ADCs Physical Number Of Bits (PNOB) and thus significantly decrease the amount of electronic hardware (and accordingly the power dissipation, occupied area on an integrated circuit and cost). For example, saving 2 bits saves approximately 75% of the power consumption. However, this solution introduces large quantization distortions, which may seriously degrade the Bit-Error-Rate (BEP) performance.
Typically the ADCs are based on uniform quantization, i.e. the threshold and output levels are uniformly distributed within the signal dynamic range. When the quantization is sufficiently fine, the quantization distortion can be modeled as uniformly distributed white noise and incorporated into the BER analysis. However, in case of low-resolution quantization (1-4 bits), the distortion becomes severe, non-linear, and deviates from the additive noise model. In turn, the effect of BER performance is less predictable, and strongly depends on the calibration of the quantization thresholds and output values.
It is therefore desirable by using DSP techniques, to allow using low-resolution, low cost and low power consumption ADCs, while improving BER performance over conventional designs for datacenter interconnects.
It is an object of the present invention to provide a method for thresholds quantization of an ADC, which is optimized jointly with the MLSE-based receivers.
It is another object of the present invention to provide a method for thresholds quantization of an ADC in MLSE-based receivers, which is optimized according to minimum BER performance.
It is a further object of the present invention to provide a method for thresholds quantization of an ADC, which allows reducing its number of bits without affecting the system BER performance.
Other objects and advantages of the invention will become apparent as the description proceeds.